This invention relates generally to computer systems and more particularly to devices used to drive signals onto and receive signals from a computer bus.
As it is known in the art, computer systems generally include a device referred to as a central processor unit which is used to execute computer instructions to perform some function. The central processing unit generally referred to as a CPU communicates with other devices in the computer system via a communications network generally referred to as a computer bus or system bus. Other devices commonly coupled to the system bus include memory systems such as main memory and more persistent type of storage systems such as magnetic disk type storage systems. These devices including the CPU are generally not connected directly to the system bus but rather are coupled to the bus through a device called a bus interface.
The bus interface device for a CPU may be quite different than that for a main memory or for a magnetic disk device. Moreover, for persistent storage such as magnetic disk, an interface module called a I/O bus adapter is often used to interface the system bus to an I/O bus (input/output bus) to which are connected several disk storage devices.
In general however, all of these interfaces on a particular bus use a common set of devices called bus drivers and bus receivers to send and receive logic signals with proper voltage levels and appropriate drive capacity to insure reliable transfers of data on the bus.
As it is also known, system buses generally carry information including address information, control information, and data. Busses transfer this information in a logical manner as determined by the design of the system. This logical manner is referred to as the bus protocol.
One problem that is common with system buses is that as CPUs process information faster, it is necessary to provide a concomitant increase in bus transfer rate to permit more address, control, and data to be transferred at correspondingly faster rates on the bus so as not to Obviate the advantages obtained by use of a faster CPU.
Buses can be so-called synchronous buses in which all transfers are synchronized to a common timing signal referred to as a clock signal or the buses can be asychronous buses in which hand-shaking signals are used to transfer information as quickly as possible.
Several problems are associated with improving bus performance whether the bus is synchronous or asychronous. A characteristic called cycle time gives an indication of the speed of a bus. For a synchronous bus, a cycle can be viewed as that period of time required to complete a transfer on the bus before a new transfer can begin. This minimum period determines the maximum clock rate.
In general, the minimum cycle time for a synchronous bus is related to noise in the clock generally referred to as clock skew, propagation delay from an asserting edge of the clock to the period of time that the data appears at the output of the device connected to the bus, and delay associated with driving the bus. The delay associated with driving the bus includes two components. The first one is the propagation delay through the bus driver and the second is the period of time necessary to have the bus settle.
For an asychronous bus similar electrical considerations are present to determine a minimum cycle time. For the asychronous bus, the minimum cycle time is related to skew between the handshaking signals, propagation delay from an asserting edge of the handshaking signals to the period of time that the data appears at the output of the device connected to the bus, and delay associated with driving the bus including the above mentioned propagation delay and settling time characteristics.
Settling time is related to inter alia the amount of time necessary to have voltage on the bus from the last state of the bus settle out so that the driver for the next state of the bus can drive voltage on the bus at the appropriate value. For example, for a "logic one" level, the driver connected to the bus typically sinks current from other devices connected to the bus, whereas for a "logic zero" the driver typically sources current onto the bus to other devices connected to the bus.
In a typical computer system, a plurality of conductors are used to provide the BUS between a plurality of interconnected devices. Each of the lines typically has a BUS driver and a BUS receiver associated with each one of the devices connected to it. Thus, in a typical computer system, one BUS driver may be required to drive several receivers coupled to the corresponding line. Moreover, some buses have Special lines which also permit multiple drivers to drive a line.
One problem with conventional driver circuits relates to the rise time and fall time characteristics of the driver circuit. In particular, the rise time characteristic is very important since the rise time of the signal, which is typically dictated by the high frequency characteristics of the output transistor of a driver, is related to the maximum BUS speed. Accordingly, when characterizing a BUS, a designer typically attempts to determine the lowest typical rise time which can be expected by that design of the driver and provides that lowest rise time as the maximum BUS speed for all buses using that type of driver. Higher rise times will not improve BUS speed but, rather, could potentially upset BUS speed timing.
In general, no special requirements are imposed to control rise time or fall time performance by a driver. Rather the natural rise time and fall time characteristics of the output transistor circuit in the driver are accepted and are used to dictate overall system BUS performance.
One approach used in the prior art to control rise time and fall time characteristics of the output transistor of the driver is to place a relatively small resistance in series with an input or gate circuit of the output transistor. The gate circuit having the added resistance provides a higher resistance-capacitance time constant in the gate circuit which has the effect of slowing down the rise time.
One problem with this approach, however, is that such resistances are generally provided as internally integrated devices within the gate circuit and the tolerances on resistance which can generally be achieved by standard semiconductor processing techniques is relatively poor, typically on the order of about 15 percent. This relatively poor tolerance provides too much variation in the rise time and fall time characteristics of the transistor to be effective in controlling rise time.
Moreover the above technique is inadequate to compensate for variations due to temperature changes, processing differences amongst different devices using such bus components and aging effects.